Research on Low Power Test Pattern Generation for Integrated Circuits

王义; 游子毅

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Research on Low Power Test Pattern Generation for Integrated Circuits

更新时间：2026-09-14

- Research on Low Power Test Pattern Generation for Integrated Circuits
- 集成电路低功耗测试生成器的研究
- Vol. 32, Issue 6, Pages: 775-779(2011)
- 作者机构：
  
  贵州师范大学物理与电子科学学院
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2011
- 稿件说明：
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王义, 游子毅. Research on Low Power Test Pattern Generation for Integrated Circuits[J]. 2011, 32(6): 775-779.
DOI：

王义, 游子毅. Research on Low Power Test Pattern Generation for Integrated Circuits[J]. 2011, 32(6): 775-779. DOI：

摘要

分析了CMOS集成电路的功耗来源

介绍了CMOS集成电路的低功耗测试向量生成器的电路结构.为了减少被测电路内部节点的开关翻转活动率

提高相邻测试向量之间的相关性

研究了随机单输入跳变测试向量生成器和基于可配置二维线性反馈移位寄存器测试向量生成器的实现方案.给出了内建自测试环境下的电路测试结构图

可以在不损失故障覆盖率的前提下

降低被测电路的开关翻转活动率

实现测试期间的低功耗

适合于CMOS集成电路的内建自测试.

Abstract

Sources of power consumption for CMOS integrated circuits were analyzed and several low power test pattern generation for CMOS integrated circuits were introduced.In order to reduce the internal switching activity rate of the circuit-under-test(CUT)

testing vector was recombined to raise the correlation between adjacent vectors.An test pattern generation construction based on the random single input change(RSIC) test pattern generation and configurable two dimensional liner feedback shifter registers(2D-LFSR) test pattern generation in BIST test structure chart were proposed

which optimizes the switching activity of circuit-under-test and then results in decreasing of test power consumption

it is suitable for BIST of CMOS integrated circuits especially.

关键词

Keywords

references

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