The resource utilization of digital filters is low by using FPGA.Based on the two-dimensional(2-D) distributed structure of FIR filter presented by Meher
some improvements were made
included adding delay modules and binary weight multiplication(*2n)to replace shift and addition structure.Two structures
"time-delaying type" and "improvement type"
were designed and implemented on FPGA with orders of 3
7
15
31
63 respectively.The Altera DE2 and AD/DA were used to test the "improvement type".The experimental results illustrated that the feasibility of the improved filter.
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references
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