An UWB Low Noise Amplifier in 0.13 μm CMOS

苏丽梅; 郝群; 马建荣

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An UWB Low Noise Amplifier in 0.13 μm CMOS

更新时间：2026-09-14

- An UWB Low Noise Amplifier in 0.13 μm CMOS
- 基于0.13μm CMOS技术的超宽带低噪放大器设计
- Vol. 34, Issue 2, Pages: 199-203(2013)
- 作者机构：
  
  1. 北京理工大学光电学院
  2. 中北大学信息与通信工程学院
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2013
- 稿件说明：
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苏丽梅, 郝群, 马建荣. An UWB Low Noise Amplifier in 0.13 μm CMOS[J]. 2013, 34(2): 199-203.
DOI：

苏丽梅, 郝群, 马建荣. An UWB Low Noise Amplifier in 0.13 μm CMOS[J]. 2013, 34(2): 199-203. DOI：

摘要

针对信号频段为3.1～10.6GHz的超宽带系统射频前端

提出一种基于0.13μm CMOS技术的低噪声放大器设计与实现.该放大器采用两级结构

通过第一级单端型电阻反馈和第二级单端转差分型电压缓冲器的级联设计

在获得足够的信号功率增益的同时

能够实现超宽带范围内的输入匹配.整体电路仿真结果表明:在3.1～10.6GHz的工作频段

电压增益为23.2dB

输入回波损耗小于-13dB.在6GHz时噪声系数最小值为2.4dB

最大值为2.7dB

输入三阶交调截取点(IIP3)为-11.9dBm.在1.2V电源电压下

该低噪声放大器功耗为12.2mW

芯片面积为0.32mm2.

Abstract

Aiming at the design of radio frequency(RF) front-end of the ultra-wideband(UWB) system with the signal frequency band of 3.1～10.6 GHz

a low noise amplifier(LNA) based on 0.13 μm CMOS technology was presented.With cascading the first stage with single-ended resistor feedback architecture and the second stage of single-to-differential voltage buffer

the proposed LNA obtained large power gain and simultaneously realized input impedance matching in the whole ultra wideband.The simulation results show a 23.2 dB voltage gain and input return loss below-13 dB from 3.1～10.6 GHz

2.4 dB and 2.7 dB minimum and maximum noise figure(NF)

and-11.9 dBm IIP3 at 6 GHz are achieved.With 1.2 V supply voltage

the wideband LNA consumes 12.2 mW.The silicon area is 0.32 mm2.

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references

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