Optimal Design of DSP-Based H.264 Decoder

胡宏华; 谌德荣

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Optimal Design of DSP-Based H.264 Decoder

更新时间：2026-09-14

- Optimal Design of DSP-Based H.264 Decoder
- 基于DSP的H.264解码器优化设计
- Vol. 32, Issue 6, Pages: 763-767(2011)
- 作者机构：
  
  北京理工大学机电学院
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2011
- 稿件说明：
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胡宏华, 谌德荣. Optimal Design of DSP-Based H.264 Decoder[J]. 2011, 32(6): 763-767.
DOI：

胡宏华, 谌德荣. Optimal Design of DSP-Based H.264 Decoder[J]. 2011, 32(6): 763-767. DOI：

摘要

针对嵌入式系统中处理器运算能力和系统资源受限的特点

提出两种提高基于通用数字信号处理器(DSP)的H.264解码器性能的优化方法.一种是适合DSP实现的预读取参考帧数据的运动补偿方法

此方法可以增加数据总线的吞吐量

提高处理器运算能力.另一种是采用基于宏块的去块效应滤波方式

该方法不但减少了DSP内核访问片外存储器的次数

而且提高了DSP内核的运行效率.测试表明

两种优化方法使解码器的平均解码速度提高60%

在526 MH z实现C IF图像解码速度达到30帧/s

完全满足实时解码要求.

Abstract

The embedded system suffers from the limitation of computing power and corresponding resources.Based on a general digital signal processor(DSP)

two kinds of optimization techniques were proposed to enhance the performance of H.264 decoder.One was to transfer data of reference frame via DMA with a novel approach

which could increase the throughputs of external bus and strengthen computing power.The other was resorted to the block-based de-blocking filter

which not only minimized the times of external memory access

but also improved efficiency of DSP core.The experimental results show that the proposed solution improves the H.264 decoding speed by almost 60%.The optimized H.264 decoder can achieve the CIF @30 Hz video decoding on a Blackfin 533 processor operating at 526 MHz

which fully meets the requirement of real-time decoding.

关键词

Keywords

references

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Hu Shuai,Zhang Zhe,Zhang Mengsu.Optimization of memory allocation for H.264/avc video decoder on digitalsignal processor[J].IEEE Computer society,2008,2:71-75.

Sihn K K,Baik H,Kim J T.Novel approaches to parallel H.264 decoder on symmetric multicore systems[J].Acoustics,Speech and Signal Processing,2009:2017-2020.

任李悦,唐宁.基于H2.64解码器的软件优化[J].电子设计工程,2009,17(12):104-105.Ren Liyue,Tang Ning.New software optimization based on H.264 decoder[J].Electronics Design Engineering,2009,17(12):104-105.(in Chinese)

Wang Shengzen,Lin Tingan,Liu Tsuming.A new motion compensation design for H.264/AVC decoder[J].Circuits and Systems,2005,5:4558-4561.

Tsai C Y,Chen T C,Chen T W.Bandwidth optimized motion compensation hardware design for H.264/AVCHDTV decoder[J].Circuits and Systems,2005,2:1199-1202.

Analog Devices,Inc.Frank.ADSP-BF533 blackfin processor hardware reference[Z].Norwood,Massachusetts,USA:Analog Devices,2009.

Pescsdor F,Garrido M J,Sanz C.A real-time H.264 MP decoder based on a DM642 DSP[J].Electronics,Circuitsand Systems,2007:1248-1251.

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