一种共享存储器的FPGA配置电路设计

马英矫; 马瑛蓬; 徐亮

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一种共享存储器的FPGA配置电路设计

更新时间：2026-09-14

- 一种共享存储器的FPGA配置电路设计
- 一种共享存储器的FPGA配置电路设计
- Issue 3, (2012)
- 作者机构：
  
  1. 南京理工大学电子工程与光电技术学院
  2. 太原理工大学机械工程学院
  3. 中北大学机械工程与自动化学院
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2012
- 稿件说明：
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马英矫, 马瑛蓬, 徐亮. 一种共享存储器的FPGA配置电路设计[J]. 2012, (3).
DOI：

马英矫, 马瑛蓬, 徐亮. 一种共享存储器的FPGA配置电路设计[J]. 2012, (3). DOI：

摘要

针对目前FPGA的USB数据下载电缆无AS配置模式和成本高的现状

根据IEEE1149.1标准

USB协议以及JTAG边界扫描原理

设计并制作了一种在QuartusⅡ环境下使用的成本较低的USB数据下载电缆.以CycloneⅢ系列的EP3C16M164作为目标器件

详细阐述了如何采用USB接口芯片

CPLD和Altera的FPGA产品专用AS配置器件设计共享存储器的配置电路

同时结合软件QuartusⅡ和FTDI公司的D2XX介绍了配置目标芯片FPGA的使用流程.经过软硬件联调的测试结果表明:可通过AS模式和JTAG模式两种配置模式配置FPGA

达到使用一块AS配置芯片可配制多块FPGA的效果.较普通USB Blaster的改进之处在于精简了AS配置芯片的数量

成本和灵活性都有很大的优势.

Abstract

The USB download cable does not support the AS configuration mode and the cost is high.A kind of low-cost USB download cable based on IEEE std.1149.1

JTAG boundary-scan principle and USB principle was designed

which can be used in the QuartusII with a higher compatible capability.Choosing EP3C16M164 which belonged to the Cyclone Ⅲ series as the target device

it was researched how to use the USB interface chip

CPLD and AS configuration Chip to design a configuration circuit based on the shared memory.In addition

how to configure target chip with the help of Quartusll and D2XX produced by FTDI was discussed.The download circuit discussed had already been proved.The experimental results illustrate that multiple FPGAs can be configured by the single AS chip through AS configuration mode and JTAG configuration mode.Compared with traditional download cab

the download circuit decreases the quantity of AS chip and has advantages in the cost and flexibility.

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