The USB download cable does not support the AS configuration mode and the cost is high.A kind of low-cost USB download cable based on IEEE std.1149.1

JTAG boundary-scan principle and USB principle was designed

which can be used in the QuartusII with a higher compatible capability.Choosing EP3C16M164 which belonged to the Cyclone Ⅲ series as the target device

it was researched how to use the USB interface chip

CPLD and AS configuration Chip to design a configuration circuit based on the shared memory.In addition

how to configure target chip with the help of Quartusll and D2XX produced by FTDI was discussed.The download circuit discussed had already been proved.The experimental results illustrate that multiple FPGAs can be configured by the single AS chip through AS configuration mode and JTAG configuration mode.Compared with traditional download cab

the download circuit decreases the quantity of AS chip and has advantages in the cost and flexibility.